I. Field of the Disclosure
The technology of the disclosure relates generally to virtually-tagged memory caches capable of containing cache entries for virtual aliased addresses.
II. Background
Virtual addressing may be employed in a computer system. In such computer systems, when performing a memory-based operation (e.g., a read or a write), a virtual address (VA) provided by the operation is translated to a physical address (PA) to perform the operation. One or more caches may be employed in such systems to reduce memory access times. In this regard, a virtually-addressed cache (VAC) may be employed in a computer system employing virtual addressing. Virtually addressed caches allow faster processing, because they do not require address translation when requested data is found in the cache. If data stored at a physical address pointed to by a virtual address that is the subject of an operation is contained in the VAC, main memory does not have to be accessed. If a VAC is also virtually-tagged, the VAC is a virtually-indexed virtually-tagged cache (VIVT cache). In a VIVT cache, a virtual address that is the subject of an operation is used to index a virtual tag stored in the VIVT cache. The virtual tag is used to determine a cache hit or cache miss for the virtual address. If a cache hit occurs, the data stored in the VIVT cache associated with the index is provided. As a result, further memory access to lower level caches or main memory is avoided.
Faster cache access times of a VIVT cache come with a cost. Architectures using a VIVT cache encounter problems with synonyms that may require costly additional circuitry and complexity to avoid incoherency issues in the VIVT cache. Synonyms may also be referred to as “virtual aliased addresses.” Virtual aliased addresses are created when two or more different virtual addresses translate to a same physical address. Because of virtual aliased addresses, a VIVT cache may generate a miss, even when data stored at the physical address corresponding to the virtual address is contained in the VIVT cache. In other words, a VIVT cache may report a false miss. This can occur, for example, when a first virtual address and a second virtual address each point to the same physical address. Consider a scenario when a tag corresponding to the first virtual address is contained in the VIVT cache, but a tag corresponding to the second virtual address is not contained in the VIVT cache. If a read operation is performed on the second virtual address, the VIVT cache will report a miss, because a tag corresponding to the second virtual address is not contained in the VIVT cache. However, the data for the physical address corresponding to the second virtual address is contained in the VIVT cache in an entry corresponding to the first virtual address. Thus, the miss generated by the VIVT cache is a false miss. For a read operation, one consequence of this false miss is a performance penalty. Because the VIVT cache reported a miss, the processing system will attempt to access the data from a secondary cache or main memory (resulting in a longer access time). Another consequence of the reported VIVT cache miss for a read operation could be data incoherency. In the event that the aliased data in the cache is dirty, the read will attempt to access the data from a secondary cache or main memory, both of which have a stale copy of the data.
For a write operation, the consequence of this false miss is data incoherency. Because the VIVT cache generates a false miss, the entry in the VIVT cache corresponding to the first virtual address (also corresponding to the same physical address as the second virtual address) will not be overwritten with the new data from the write operation. The write operation will cause other memory (e.g., an entry corresponding to the physical address in a secondary cache and/or main memory) to store the new data. However, a subsequent read operation performed on the first physical address would result in the VIVT cache returning incorrect data (the old data) no longer stored at the corresponding physical address.